1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to electrically programmable fuses (e-fuses) and methods of manufacturing thereof.
2. Description of the Related Art
Transistors are the dominant components in modern electronic devices. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit have as small as possible typical dimensions, so as to enable a high integration density.
One of the most widespread technologies is the complementary metal-oxide-semiconductor (CMOS) technology, wherein complementary field-effect transistors (FETs), i.e., P-channel FETs and N-channel FETs, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies.
Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials such as, for example, dopant atoms or ions may be introduced into the original semiconductor layer.
When fabricating transistors with typical gate dimensions below 50 nm, the so-called “high-k/metal gate” (HKMG) technology has by now become the new manufacturing standard. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. This is in contrast to the conventional oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride, in the case of silicon-based devices.
Currently, two different approaches exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages, such as dopant ion implantation, source and drain region formation and substrate silicidation, are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high temperature source/drain formation and all silicide annealing cycles have been carried out.
HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel typical sizes as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges and requires new integration schemes with respect to the conventional poly/SiON technology.
For example, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level.
Furthermore, in the HKMG technology, a thin “work function metal” layer is inserted between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage can thus be adjusted by varying the thickness of the metal layer. The gate metal layer may comprise, for example, tantalum (Ta), tungsten (W), titanium nitride (TiN) or tantalum nitride (TaN). On the other hand, the work function metal layer may comprise metals such as aluminum and lanthanum. Work function metals may also be included in the gate metal layer.
According to the gate-first HKMG approach, the gate structure is formed by depositing a stack of layers, which is subsequently appropriately patterned so as to obtain a gate structure of the desired size and dimensions. The stack includes the high-k material layer formed on the surface of the substrate, the gate metal layer formed above the high-k material layer, and a gate material layer formed on top of the gate metal layer.
Since the gate material layer is usually comprised of a semiconductor, for example polysilicon, a Schottky barrier is established at the interface between the gate metal layer and the gate semiconductor material. This undesirably degrades the AC performance of a semiconductor device by limiting the circuit switching speed.
A method of solving the problem of the Schottky barrier is forming a so-called “fully silicided” gate, i.e., a gate structure wherein the metal silicide completely replaces the semiconductor gate material, so as to directly form an interface with the gate metal layer. An example of a manufacturing method of a fully silicided metal gate can be found in U.S. Pat. No. 6,821,887.
Reducing the typical dimensions of integrated circuits also leads to an increased probability of failure of single chip components, which in turn results in a decrease of product yield. Typically, a damage of a component such as a single metal link, a transistor or a resistor causes the entire integrated circuit to be unusable. This is obviously in contrast with the semiconductor industry endeavor of achieving ever increasing product quality, reliability and throughput.
In order to improve the product yield, a technique has been developed of “trimming” or electrically excluding circuit blocks which are no longer operable. This technique, particularly used during manufacturing of memory arrays, relies on redundant circuit blocks which can be incorporated into the main integrated circuit and activated once a defective circuit portion has been detected. On the other hand, the defective circuit block may be trimmed or electrically removed by blowing a fuse or a group of fuses which can electrically disconnect the defective block from the main circuit when in the open configuration. Reprogramming of an integrated circuit is thus rendered possible in a dynamic manner, even after the chip has been manufactured.
One of the most successfully used types of fuses used for enabling dynamic chip reprogramming is the so-called electrically programmable fuse (e-fuse). The cross-section of a typical e-fuse 100 formed during a manufacturing flow according to the HKMG technology is shown in FIG. 1a. 
An e-fuse 100 is formed on an isolation region 112 of a substrate (not shown). The substrate may be any appropriate carrier for a semiconductor integrated device. The isolation region 112 may, for example, have been formed by means of shallow trench isolation (STI). The e-fuse 100 includes a metal layer 124 formed above the surface of the isolation region 112. The material or material mixture constituting the layer 124 are typically the same as the material or material mixture making up the gate metal layer in the HKMG technology. Although not shown in the figure, a high-k dielectric layer may be interposed between the metal layer 124 and the surface of the isolation region 112.
A semiconductor layer 144 is then formed on the metal layer 124. The semiconductor material forming the layer 144 is preferably the same material used for forming the gate material layer on the gate metal layer. Thus, the semiconductor layer 144 is usually comprised of polysilicon. A metal silicide layer 164, typically nickel silicide, is finally formed on the surface of the semiconductor layer 144. The metal silicide layer 164 is conveniently formed during the same silicidation process used for forming electrical contacts to the electrodes (gate, source and drain) of a FET.
The metal silicide layer 164 includes a first electrode 164a and a second electrode 164c arranged at opposite ends of the layer 164. The first electrode 164a and the second electrode 164c could, for example, be the anode and the cathode of the e-fuse 100. Contact terminals 174a and 174b are then formed so as to provide an electrical connection to the first electrode 164a and the second electrode 164c, respectively. Contact terminals 174a and 174b are typically comprised of a metal with a high electrical conductivity.
When the e-fuse 100 is un-programmed, the metal silicide layer 164 is continuous and provides an electrical connection between the first electrode 164a and the second electrode 164b, thus presenting a low electrical resistance between terminals 174a and 174b. The e-fuse 100 may then be programmed by applying a predetermined electrical bias between terminals 174a and 174b, thereby inducing a current to flow across the e-fuse 100. Since the resistivity of the semiconductor layer 144 is much greater than that of the silicide layer 164, almost all current flows through the latter layer. If the current intensity exceeds a predetermined threshold, electromigration occurs in the silicide layer 164, resulting in transport of the metal silicide material constituting the layer 164 towards the anode. After a sufficient amount of material has been transferred to one of the two electrodes 164a and 164c representing the anode, the e-fuse 100 switches to the programmed state when a gap is formed in the metal silicide layer 164, thereby resulting in an open circuit between the two terminals 174a and 174b. The electrical resistance of the programmed e-fuse 100 thus rises by several orders of magnitude with respect to the resistance in the un-programmed state.
A problem arises when the e-fuse 100 is formed in the course of an HKMG manufacturing flow, wherein fully-silicided metal gate FETs are formed in the integrated circuit. In this case, an electrical contact is likely established between the topmost metal silicide layer 164 and the lower-lying metal layer 124 of the e-fuse 100, with extremely harmful consequences on the correct functioning of the e-fuse 100. In case of an electrical contact between the metal silicide layer 164 and metal layer 124, a substantial amount of current would flow through the metal layer 124, thus preventing the desired electromigration in the metal silicide layer 164 from taking place. This is mainly due to current crowding in the metal layer 124. The e-fuse 100 could, therefore, not be blown by inducing a current of a desired intensity and the desired high resistance between the first electrode 164a and the second electrode 164c cannot be achieved.
A need then arises for an e-fuse with an improved design and produced by means of a manufacturing flow which can be easily integrated in the HKMG manufacturing flow. Especially, an e-fuse would be desirable which can be efficiently manufactured during a HKMG manufacturing flow resulting in a fully silicided gate.